1. Field of the Invention
The present invention relates to a fault analysis technology for a semiconductor integrated circuit (IC). More specifically, the present invention relates to a technique for identifying, from among a large number of paths in the semiconductor IC, path having appropriate lengths for a fault simulation.
2. Description of the Related Art
A high-speed, high-performance, and high-density system LSI, which has been developed along with the recent progress in the semiconductor process technology, is likely to suffer from small-delay faults. Accordingly, detection technology for such a delay fault is strongly needed.
In a delay fault, a signal transition occurs but the timing thereof is delayed. Two delay tests for the detection of delay fault have been proposed. The first is a path-delay-fault test in which all the paths in a semiconductor IC are tested. The second is a transition test in which test patterns for paths that are easy to activate are generated on the assumption that there is a serious delay fault in the signal transition on a specific signal line.
On the other hand, a test-pattern generation technique, such as Japanese Patent Laid-Open No. 2004-150820, has been suggested in which a test vector for a specific area of the semiconductor IC is generated.
However, according to the conventional technology disclosed in Japanese Patent Laid-Open No. 2004-150820, the test vector is generated for a path on which static timing analysis (STA) has been executed using circuit data of the semiconductor IC. In STA, only top few hundreds of long paths (critical paths) that affect the speed of the semiconductor IC are tested. As a result, it is difficult to detect all of the delay faults that might occur at any location in the semiconductor IC, which resulting in a poor reliability of the semiconductor IC.
On the other hand, it takes an extremely long time to detect delay faults for all of the paths in the semiconductor IC, which resulting in a longer production time of the semiconductor IC.